A flash memory including a memory cell which is able to secure a sufficiently large amount of capacity between a charge-storage layer and a control gate in a small occupancy area on a substrate, achieving a superior writing and deleting efficiency, and having the charge-storage layer and the control gate formed on a side wall of an island semiconductor layer formed on the surface of a semiconductor substrate so as to surround the island semiconductor layer is proposed (for example, see JP-A-8-148587 and Howard Pein, et. al, IEEE Electron Device Letters, Vol. 14, No. 8, pp. 415-pp. 417, 1993).
In the flash memory described above, injection of electric charge to the charge-storage layer is carried out using hot electrons. The differences of threshold voltages according to the difference of the charge storage state of the charge-storage layer are stored as data “0”, “1”. For example, in the case of an N-channel memory cell using a floating gate for the charge-storage layer, a high voltage is applied to the control gate and a drain diffusion layer, and a source diffusion layer and the semiconductor substrate are grounded when injecting electric charge to the floating gate. At this time, the electric charge is injected by enhancing electronic energy of the semiconductor substrate by the voltage between a source and a drain to allow the electric charge to surmount an energy barrier of a tunnel oxide film and to be injected to the electric-storage layer. As a result of the injection of the electric charge, a threshold voltage of the memory cell moves in the normal direction. The percentage of a current flowing between the source and the drain which is injected into the charge-storage layer is low. Therefore, the current required for writing is on the order of 100 μA per cell. In the case of NOR type flash memories, a current flowing during reading is on the order of 30 μA.
A flash memory cell array including the memory cell using the side wall of the island semiconductor layer employs a diffusion layer as a source line or a source surface. The diffusion layer has higher resistance than metal. When a current flows in the resistance, a potential difference is generated. Therefore, at the time of writing, the voltage of the source diffusion layer of the memory cell assumes a voltage higher than 0V, the voltage between the source and the drain is lowered, the current flowing between the source and drain is reduced, and the writing speed is lowered. At the time of reading as well, the voltage of the source diffusion layer of the memory cell assumes a voltage higher than 0V, the voltage between the source and the drain is lowered, a current flowing between the source and drain is reduced, and the reading speed is lowered.